STLS2F Loongson 2F high performance bit superscalar MIPS. ® microprocessor. Features. □ bit superscalar architecture. □ MHz clock frequency. Loongson 2F: High performance bit superscalar MIPS. ® microprocessor. Features. □ bit superscalar architecture. □ MHz clock. ICT Loongson 2F (ST STLS2F01) (Godson-2). ICT Loongson 2F ( MHz) (90 nm) + MB of DDR2. Lemote YeeLoong notebook. 4-way superscalar.

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Archived from the original on 15 September Loongson is the result of a public—private partnership. It may also get the data directly from one of the result buses if its source register number matches the destination register number of the result bus. Based in BeijingLoongspn focuses on designing the bit Loongson general-purpose and embedded processors, together with developing software tools and reference platforms.

Early implementations of the family lacked four instructions patented by MIPS Technologies to avoid legal issues. Loongsson version can be clocked from 1.

The topic of the speech was “Research and Development of Godson processors”. For the performance, because the frequency is only 1. Archived from the original on 23 April In other projects Wikimedia Commons. Many operating systems work on Loongson: They are also sent to the memory access queue to allow committed store instructions to write cache or memory.

Loongson 2F MHz vs MediaTek MT V/A GHz

Instructions are executed according to its type and execution results are written back to the register file. The issued instruction reads its source operands from the physical register file and is sent to the associated functional units. June Learn how and when to remove this template looongson. As one of the domestic CPU of China, Loongson 3A is being commercialized, and in the recently exhibition in Nanjingbased on the Loongson 3A motherboard developers computer quietly debut.


China enters the low-cost laptop competition. Loongson insiders [56] revealed a new model based on the Loongson 3A quad-core laptop has been developed and is expected to launch in August The manufacturer states that the user experience of the desktop solution has been significantly improved over its Loongson-3A based predecessor.

Package: linux-image-loongson-2f (3.16+63+deb8u2)

This page was last edited on 2 Decemberat Open source applications on Linux Platform can be ported with little effort. In SeptemberLemote announced the Yeeloong Retrieved 16 April Please improve this article by removing excessive or inappropriate external links, and converting useful links where appropriate into footnote references. Retrieved 26 May It is fabricated with 0.

This article’s use of external links may not follow Wikipedia’s policies or guidelines. When there are multiple instructions ready for the same functional unit, the oldest one is selected.

Retrieved 31 May Renamed instructions are dispatched to the fixed- or floating-point reservation station to be executed, and are sent to the reorder queue for in-order graduation. The new instructions help with emulation performance, for example QEMU the only known example. From Wikipedia, the free encyclopedia. Views Read Edit View history. This list is incomplete ; you can help by expanding it. Inter-instruction dependencies among four instructions mapped in the same cycle loongwon also checked.

The high-performance Dawningwhich has a projected speed of over one quadrillion operations per second, will incorporate the Loongson processor as its core.

Instructions with unready source operands snoop result and forward buses for their operands. InLoongson released latest version of 3A cpu, 3A It was formerly called Godson. Four new instructions are sent to the instruction register IR if the instruction fetch is 2v TLB hit and a cache hit.


Archived from the original on 23 October The Loongson 2 adds bit ability to the Loongson architecture.

Archived from the original on 13 April Result buses are also sent to the reservation station for snooping and to the register mapping table to notify that the associated physical register is ready. Li Guojie, chairman of Dawning Information Industry Company and director and academician of the Institute of Computing Technology, said research and development of the Dawning is expected to be completed in two years.

One instruction with all liongson operands ready is selected from the fixed- or floating-point reservation station for each functional unit.

Loongson – Wikipedia

Archived from the original on 4 June Retrieved from ” https: By using this site, you agree to the Terms of Use and Privacy Policy. Archived from the original on 21 June The value is then sent to memory access queue, where dynamic memory disambiguation and memory forwarding is performed.

Archived from the original on 9 May Broadcom various Cavium Octeon.

Marvell 88E “Link Street”. Associated instructions are also sent to branch queue and memory queue. The renamed instructions are latched lopngson be sent to reservation stations and queues in next cycle.